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12-bit quad voltage output digital-to-analog converter dac7724 dac7725 description the dac7724 and dac7725 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12-bit monotonic performance over the specified tem- perature range. they accept 12-bit parallel input data, have double-buffered dac input logic (allowing simul- taneous update of all dacs), and provide a readback mode of the internal input registers. an asynchronous reset clears all registers to a mid-scale code of 800 h (dac7724) or to a zero-scale of 000 h (dac7725). the dac7724 and dac7725 can operate from a single +15v supply, or from +15v and C15v supplies. low power and small size per dac make the dac7724 and dac7725 ideal for automatic test equipment, dac-per-pin programmers, data acquisition systems, and closed-loop servo-control. the dac7724 and dac7725 are available in a plcc-28 or a so-28 package, and offer guaranteed specifications over the C40 c to +85 c temperature range. features l low power: 250mw max l single supply output range: +10v l dual supply output range: 10v l settling time: 10 m s to 0.012% l 12-bit linearity and monotonicity: C40 c to +85 c l reset to mid-scale (dac7724) or zero-scale (dac7725) l data readback l double-buffered data inputs applications l process control l closed-loop servo-control l motor control l data acquisition systems ? 1999 burr-brown corporation pds-1517b printed in u.s.a. april, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 dac a dac register a input register a i/o buffer control logic dac b dac register b input register b dac c dac register c input register c dac d dac register d input register d v refh v cc v dd v ss v outd v outc v outb v outa v refl reset ldac gnd a0 a1 r/w cs db0-db11 12 for most current data sheet and other product information, visit www.burr-brown.com dac7724 dac7725
2 dac7724, 7725 specification (dual supply) at t a = C40 c to +85 c, v cc = +15v, v dd = +5v, v ss = C15v, v refh = +10v, v refl = C10v, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. dac7724n, u DAC7724NB, ub dac7725n, u dac7725nb, ub parameter conditions min typ max min typ max units accuracy linearity error 2 1 lsb (1) linearity matching (2) 2 1 lsb differential linearity error 1 1 lsb monotonicity t min to t max 12 [ bits zero-scale error code = 000 h 2 [ lsb zero-scale drift 1 [ ppm/ c zero-scale matching (2) 2 1 lsb full-scale error code = fff h 2 [ lsb full-scale matching (2) 2 1 lsb power supply sensitivity at full scale 10 [ ppm/v analog output voltage output (3) v refl v refh [[ v output current 5 [[ ma load capacitance no oscillation 500 [ pf short-circuit current 20 [ ma short-circuit duration to v ss , v cc , or gnd indefinite [ reference input v refh input range v refl +1.25 +10 [[ v v refl input range C10 v refh C 1.25 [[ v ref high input current C0.5 3.0 [[ ma ref low input current C3.5 0 [[ ma dynamic performance settling time to 0.012%, 20v output step 8 10 [[ m s channel-to-channel crosstalk full-scale step 0.25 [ lsb digital feedthrough 2 [ nv-s output noise voltage f = 10khz 65 [ nv/ ? hz digital input/output logic family ttl-compatible cmos [ logic levels v ih i ih 10 m a 2.4 v dd +0.3 [[ v v il i il 10 m a C0.3 0.8 [[ v v oh i oh = C0.8ma 3.6 v dd [[ v v ol i ol = 1.6ma 0.0 0.4 [[ v data format straight binary [ power supply requirements v dd +4.75 +5.25 [[ v v cc +14.25 +15.75 [[ v v ss C14.25 C15.75 [[ v i dd 50 [[ m a i cc 6 8.5 [[ ma i ss C8 C6 [[ ma power dissipation 180 250 [[ mw temperature range specified performance C40 +85 [[ c notes: (1) lsb means least significant bit, when v refh equals +10v and v refl equals C10v, then one lsb equals 4.88mv. (2) all dac outputs will match within the specified error band. (3) ideal output voltage, does not take into account zero or full-scale error.
3 dac7724, 7725 specification (single supply) at t a = C40 c to +85 c, v cc = +15v, v dd = +5v, v ss = gnd, v refh = +10v, v refl = 0v, unless otherwise noted. dac7724n, u DAC7724NB, ub dac7725n, u dac7725nb, ub parameter conditions min typ max min typ max units accuracy linearity error (1) 2 1 lsb (2) linearity matching (3) 2 1 lsb differential linearity error 1 1 lsb monotonicity t min to t max 12 [ bits zero-scale error code = 004 h 4 [ lsb zero-scale drift 2 [ ppm/ c zero-scale matching (3) 4 2 lsb full-scale error code = fff h 4 [ lsb full-scale matching (3) 4 2 lsb power supply sensitivity at full scale 20 [ ppm /v analog output voltage output (4) v refl v refh [[ v output current 5 [ ma load capacitance no oscillation 500 [ pf short-circuit current 20 [ ma short-circuit duration to v cc or gnd indefinite [ reference input v refh input range v refl +1.25 +10 [[ v v refl input range 0 v refh C 1.25 [[ v ref high input current C0.3 1.5 [[ ma ref low input current C2.0 0 [[ ma dynamic performance settling time (5) to 0.012%, 10v output step 8 10 [[ m s channel-to-channel crosstalk 0.25 [ lsb digital feedthrough 2 [ nv-s output noise voltage f = 10khz 65 [ nv/ ? hz digital input/output logic family ttl-compatible cmos [ logic levels v ih i ih 10 m a 2.4 v dd +0.3 [[ v v il i il 10 m a C0.3 0.8 [[ v v oh i oh = C0.8ma 3.6 v dd [[ v v ol i ol = 1.6ma 0.0 0.4 [[ v data format straight binary [ power supply requirements v dd +4.75 +5.25 [[ v v cc 14.25 15.75 [[ v i dd 50 [[ m a i cc 3.0 [[ ma power dissipation 45 [ mw temperature range specified performance C40 +85 [[ c notes: (1) if v ss = 0v, specification applies at code 004 h and above. (2) lsb means least significant bit, when v refh equals +10v and v refl equals 0v, then one lsb equals 2.44mv. (3) all dac outputs will match within the specified error band. (4) ideal output voltage, does not take into account zero or full-scale error. (5) full-scale positive 10v step and negative step from code fff h to 004 h .
4 dac7724, 7725 refh v ss v cc v dd v cc v ss v dd gnd v out refl 1 of 4 typ of each logic input pin typ of each i/o pin absolute maximum ratings (1) v cc to v ss ........................................................................... C0.3v to +32v v cc to gnd ......................................................................... C0.3v to +16v v ss to gnd ......................................................................... +0.3v to C16v v dd to gnd ............................................................................. C0.3v to 6v v ref h to gnd ....................................................................... C9v to +11v v ref l to gnd (v ss = C15v) ................................................. C11v to +9v v ref l to gnd (v ss = 0v) .................................................... C0.3v to +9v v refh to v refl ....................................................................... C1v to +22v digital input voltage to gnd ................................... C0.3v to v dd + 0.3v digital output voltage to gnd ................................. C0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ........................................ C40 c to +85 c storage temperature range ......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information maximum maximum linearity differential package specification error nonlinearity error drawing temperature ordering transport product (lsb) (lsb) package number range number (1) media dac7724n 2 1 plcc-28 251 C40 c to +85 c dac7724n rails "" " " " " dac7724n/750 tape and reel DAC7724NB 1 1 plcc-28 251 C40 c to +85 c DAC7724NB rails "" " " " " DAC7724NB/750 tape and reel dac7724u 2 1 so-28 217 C40 c to +85 c dac7724u rails "" " " " " dac7724u/1k tape and reel dac7724ub 1 1 so-28 217 C40 c to +85 c dac7724ub rails "" " " " " dac7724ub/1k tape and reel dac7725n 2 1 plcc-28 251 C40 c to +85 c dac7725n rails "" " " " " dac7725n/750 tape and reel dac7725nb 1 1 plcc-28 251 C40 c to +85 c dac7725nb rails "" " " " " dac7725nb/750 tape and reel dac7725u 2 1 so-28 217 C40 c to +85 c dac7725u rails "" " " " " dac7725u/1k tape and reel dac7725ub 1 1 so-28 217 C40 c to +85 c dac7725ub rails "" " " " " dac7725ub/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /750 indicates 750 dev ices per reel). ordering 750 pieces of dac7724/750 will get a single 750-piece tape and reel. esd protection circuits
5 dac7724, 7725 top view pin configurations pin descriptions pin name description 1v refh reference input voltage high. sets maximum output voltage for all dacs. 2v outb dac b voltage output. 3v outa dac a voltage output. 4v ss negative analog supply voltage, 0v or C15v. 5 gnd ground. 6 reset asynchronous reset input. sets dac and input registers to either mid-scale (800 h , dac7724) or zero-scale (000 h , dac7725) when low. 7 ldac load dac input. all dac registers are transparent when low. 8 db0 data bit 0. least significant bit of 12-bit word. 9 db1 data bit 1 10 db2 data bit 2 11 db3 data bit 3 12 db4 data bit 4 13 db5 data bit 5 14 db6 data bit 6 15 db7 data bit 7 16 db8 data bit 8 17 db9 data bit 9 18 db10 data bit 10 19 db11 data bit 11. most significant bit of 12-bit word. 20 r/w read/write control input (read = high, write = low). 21 a1 register/dac select (c or d = high, a or b = low). 22 a0 register/dac select (b or d = high, a or c = low). 23 cs chip select input. 24 v dd positive digital supply, +5v. 25 v cc positive analog supply voltage, +15v nominal. 26 v outd dac d voltage output. 27 v outc dac c voltage output. 28 v refl reference input voltage low. sets minimum output voltage for all dacs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v refh v outb v outa v ss gnd reset ldac (lsb) db0 db1 db2 db3 db4 db5 db6 v refl v outc v outd v cc v dd cs a0 a1 r/w db11 (msb) db10 db9 db8 db7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dac7724 dac7725 gnd reset ldac (lsb) db0 db1 db2 db3 5 6 7 8 9 10 11 25 24 23 22 21 20 19 v cc v dd cs a0 a1 r/w db11 (msb) v ss v outa v outb v refh v refl v outc v outd db4 db5 db6 db7 db8 db9 db10 4 3 2 1 28 27 26 12 13 14 15 16 17 18 dac7724 dac7725 so plcc
6 dac7724, 7725 typical performance curves: v ss = 0v at t a = +25 c, v cc = +15v, v dd = +5v, v ss = 0v, v refh = +10v, v refl = 0v, representative unit, unless otherwise specified. 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel 25 c (typical of each output channel) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel 85 c (typical of each output channel) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel ?0 c (typical of each output channel) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb) ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ?0 temperature ( c) zero-scale error vs temperature (code 004 h ) zero-scale error (mv) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dac a dac b dac c dac d ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ?0 temperature ( c) full-scale error vs temperature (code fff h ) full-scale error (mv) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dac a dac b dac c dac d 1.2 1.0 0.8 0.6 0.4 0.2 0 ?.2 ?.4 0 ?.2 ?.4 ?.6 ?.8 ?.0 ?.2 ?.4 ?.6 v ref current (ma) v ref current (ma) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h current vs code all dacs sent to indicated code v refh v refl
7 dac7724, 7725 typical performance curves: v ss = 0v (cont.) at t a = +25 c, v cc = +15v, v dd = +5v, v ss = 0v, v refh = +10v, v refl = 0v, representative unit, unless otherwise specified. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?.5 power supply current vs temperature quiescent current (ma) temperature ( c) ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 100 i dd i cc i dd i cc positive supply current vs digital input code 3.00 2.50 2.00 1.50 1.00 0.50 0 i cc (ma) no load 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 000 h digital input code output voltage mid-scale glitch performance time (1 s/div) 800 h to 7ff h +5v ldac 0 output voltage (200mv/div) output voltage mid-scale glitch performance time (1 s/div) 7ff h to 800 h +5v ldac 0 output voltage (200mv/div) output voltage vs settling time (+10v to 0v) time (2 s/div) large signal settling time: 5v/div +5v ldac 0 small signal settling time: 1lsb/div output voltage output voltage vs settling time (0v to +10v) large signal settling time: 5v/div small signal settling time: 1lsb/div +5v ldac 0 output voltage time (2 s/div)
8 dac7724, 7725 typical performance curves: v ss = 0v (cont.) at t a = +25 c, v cc = +15v, v dd = +5v, v ss = 0v, v refh = +10v, v refl = 0v, representative unit, unless otherwise specified. +15v +5v power supply rejection ratio vs frequency frequency (hz) psrr (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 10 2 10 3 10 4 10 5 10 6 10 1 single supply current limit vs input code 20 15 10 5 0 ? ?0 ?5 ?0 i out (ma) 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 000 h digital input code short to ground short to v cc 16 14 12 10 8 6 4 2 0 r load (kw) 0.01 0.1 1 10 100 output voltage vs r load v out (v) source sink logic supply current vs logic input level for data bits logic input level for data bits (v) logic supply current (ma) 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 4.5 5.0 4.0 output noise vs frequency frequency (khz) noise (nv/ hz) 1000 100 10 0.1 1 10 100 1000 10000 0 code 004 h code fff h
9 dac7724, 7725 typical performance curves: v ss = C15v at t a = +25 c, v cc = +15v, v dd = +5v, v ss = C15v, v refh = +10v, v refl = C10v, representative unit, unless otherwise specified. ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ?0 temperature ( c) positive full-scale error vs temperature (code fff h ) positive full-scale error (mv) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dac a dac b dac c dac d ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ?0 temperature ( c) bipolar zero-scale error vs temperature (code 800 h ) bipolar zero-scale error (mv) dac a dac b dac c dac d 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.5 2.0 1.5 1.0 0.5 0 ?.5 v ref current (ma) current vs code all dacs sent to indicated code v refh v refl 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e000 h fff h 0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 v ref current (ma) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel ?0 c (typical of each output channel) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel 85 c (typical of each output channel) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h linearity error and differential linearity error vs code single channel 25 c (typical of each output channel) 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 le (lsb) dle (lsb)
10 dac7724, 7725 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v cc = +15v, v dd = +5v, v ss = C15v, v refh = +10v, v refl = C10v, representative unit, unless otherwise specified. output voltage vs settling time (+10v to ?0v) time (2 s/div) +5v ldac 0 small signal settling time: 0.5lsb/div large signal settling time: 5v/div output voltage output voltage vs settling time (?0v to +10v) time (2 s/div) +5v ldac 0 small signal settling time: 0.5lsb/div large signal settling time: 5v/div output voltage 15 10 5 0 ? ?0 ?5 r load (k ) 0.01 0.1 1 10 100 output voltage vs r load v out (v) sink source supply current vs code 6 5 4 3 2 1 0 ? ? ? ? ? ? supply current (ma) i dd i ss 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 000 h digital input code data = fff h (all dacs) no load i cc 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? data = fff h (all dacs) no load power supply current vs temperature quiescent current (ma) temperature ( c) ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 i cc i dd i ss ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ?0 temperature ( c) negative full-scale error vs temperature (code 000 h ) negative full-scale error (mv) dac a dac b dac c dac d 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0
11 dac7724, 7725 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v cc = +15v, v dd = +5v, v ss = C15v, v refh = +10v, v refl = C10v, representative unit, unless otherwise specified. broadband noise time (1ms/div) noise voltage (500 m v/div) bw = 1mhz code = 800 h output voltage mid-scale glitch performance time (1 s/div) +5v ldac 0 output voltage (200mv/div) 7ff h to 800 h 800 h to 7ff h ?5v +5v power supply rejection ratio vs frequency frequency (hz) psrr (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 10 2 10 3 10 4 10 5 10 6 10 1 +15v dual supply current limit vs input code short to ground 20 15 10 5 0 ? ?0 ?5 ?0 i out (ma) 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 000 h digital input code noise at any code output noise vs frequency frequency (khz) noise (nv/ hz) 1000 100 10 0.1 1 10 100 1000 10000 0 data bus feedthrough glitch time (0.5 s/div) +5v data bus 0 output voltage (20mv/div)
12 dac7724, 7725 theory of operation the dac7724 and dac7725 are quad voltage output, 12-bit digital-to-analog converters (dacs). the architecture is a classic r-2r ladder configuration followed by an opera- tional amplifier that serves as a buffer, as shown in figure 1. each dac has its own r-2r ladder network and output op- amp, but all share the reference voltage inputs. the mini- mum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage refer- ences (v refl and v refh , respectively). the digital input is a 12-bit parallel word and the dac input registers offer a readback capability. the converters can be powered from a single +15v supply or a dual 15v supply. each device offers a reset function which immediately sets all dac registers and dac output voltages to mid-scale (dac7724, code 800 h ) or to zero-scale (dac7725, code 000 h ). see figures 2 and 3 for the basic operation of the dac7724/25. figure 1. dac7724/25 architecture. figure 2. basic single-supply operation of the dac7724/25. r 2r 2r 2r 2r 2r 2r 2r 2r 2r v ref h v out rrrrrr v ref l r f 1 2 3 4 v refh v outb load dac registers reset dacs (1) v outa v ss 5 gnd 6 reset 7 8 9 10 11 12 13 14 ldac db0 db1 db2 db3 db4 db5 db6 v refl v outc dac7724 dac7725 v outd v cc 28 27 26 25 v dd 24 cs 23 a0 a1 r/w db11 db10 db9 db8 db7 22 21 20 19 18 17 16 15 chip select read/write data bus data bus address bus or decoder +15v note: (1) reset low sets all dacs to code 800 h on the dac7724 and to code 000 h on the dac7725. 0v to +10v 0v to +10v 0v to +10v 0v to +10v 0.1 f 1 f to 10 f + +5v 0.1 f 1 f to 10 f + +10.00v 0.1 f
13 dac7724, 7725 analog outputs when v ss = C15v (dual supply operation), the output amplifier can swing to within 4v of the supply rails, guar- anteed over the C40 c to +85 c temperature range. with v ss = 0v (single-supply operation) and r load connected to ground, the output can swing to ground. note that the settling time of the output op-amp will be longer with voltages very near ground. additionally, care must be taken when measuring the zero-scale error when v ss = 0v. since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (000 h , 001 h , 002 h , etc.) if the output amplifier has a nega- tive offset. at the negative offset limit of C4 lsb (-9.76mv), for the single-supply case, the first specified output starts at code 004 h . reference inputs for dual-supply operation, the reference inputs, v refl and v refh , can be any voltage between v ss + 4v and v cc C 4v provided that v refh is at least 1.25v greater than v refl . for single-supply operation (v ss = 0v), v refl value can be above 0v, with the same provision that v refh is at least 1.25v greater than v refl . the minimum output of each dac is equal to v refl plus a small offset voltage (essen- tially, the offset of the output op-amp). the maximum output is equal to v refh plus a similar offset voltage. note that v ss (the negative power supply) must either be con- nected to ground or must be in the range of C14.25v to C15.75v. the voltage on v ss sets several bias points within the converter, if v ss is not in one of these two configura- tions, the bias values may be in error and proper operation of the device is not guaranteed. the current into the v ref h input and out of v ref l depends on the dac output voltages and can vary from a few microamps to approximately 0.3ma. the reference input appears as a varying load to the reference. if the reference can sink or source the required current, a reference buffer is not required. see reference current vs code in the typi- cal performance curves. the analog supplies (or the analog supplies and the refer- ence power supplies) have to come up first. if the power supplies for the references come up first, then the v cc and v ss supplies will be powered from the reference via the esd protection diodes (see page 4). bypassing the reference voltage or voltages with at least a 0.1uf capacitor placed as close to the dac7724/25 package is strongly recommended. figure 3. basic dual-supply operation of the dac7724/25. 1 2 3 4 v refh v outb load dac registers reset dacs (1) v outa v ss 5 gnd 6 reset 7 8 9 10 11 12 13 14 ldac db0 db1 db2 db3 db4 db5 db6 v refl v outc dac7724 dac7725 v outd v cc 28 27 26 25 v dd 24 cs 23 a0 a1 r/w db11 db10 db9 db8 db7 22 21 20 19 18 17 16 15 chip select ?0v to +10v ?0v to +10v read/write data bus address bus or decoder note: (1) reset low sets all dacs to code 800 h on the dac7724 and to code 000 h on the dac7725. ?0.000v 0.1 f ?0v to +10v ?0v to +10v ?5v +10.000v 0.1 f 0.1 f 1 f to 10 f + data bus +15v 0.1 f 1 f to 10 f + +5v 0.1 f 1 f to 10 f +
14 dac7724, 7725 v out = v refl + v refh v refl () n 4096 state of selected selected state of input input all dac a1 a0 r/w cs reset ldac register register registers l (1) lllh (2) l a transparent transparent l h l l h l b transparent transparent h l l l h l c transparent transparent h h l l h l d transparent transparent llllh h a transparent latched l h l l h h b transparent latched h l l l h h c transparent latched h h l l h h d transparent latched l l h l h h a readback latched l h h l h h b readback latched h l h l h h c readback latched h h h l h h d readback latched x (3) x x h h l none (all latched) transparent x x x h h h none (all latched) latched xxxxl x all reset (4) reset (4) notes: (1) l = logic low. (2) h= logic high. (3) x = dont care. (4) dac7724 resets to 800 h , dac7725 resets to 000 h . when reset rises, all registers that are in their latched state retain the reset value. table i. dac7724 and dac7725 control logic truth table. digital interface table i shows the basic control logic for the dac7724/25. note that each internal register is level triggered and not edge triggered. when the appropriate signal is low, the register becomes transparent. when this signal is returned high, the digital word currently in the register is latched. the first set of registers (the input registers) are triggered via the a0, a1, r/w, and cs inputs. only one of these registers is transparent at any given time. the second set of registers (the dac registers) are all transparent when ldac input is pulled low. each dac can be updated independently by writing to the appropriate input register and then updating the dac register. alternatively, the entire dac register set can be configured as always transparent by keeping ldac low the dac update will occur when the input register is written. the double buffered architecture is mainly designed so that each dac input register can be written at any time and then all dac output voltages updated simultaneously by pulling ldac low. it also allows a dac input register to be written to at any point and the dac voltage to be synchro- nously changed via a trigger signal connected to ldac. digital timing figure 4 and table ii provide detailed timing for the digital interface of the dac7724 and dac7725. digital input coding the dac7724 and dac7725 input data is in straight binary format. the output voltage is given by the following equa- tion: where n is the digital input code. this equation does not include the effects of offset (zero-scale) errors.
15 dac7724, 7725 symbol description min typ max units t rcs cs low for read 200 ns t rds r/w high to cs low 10 ns t rdh r/w high after cs high 10 ns t dz cs high to data bus in high impedance 100 ns t csd cs low to data bus valid 100 160 ns t wcs cs low for write 50 ns t ws r/w low to cs low 0 ns t wh r/w low after cs high 0 ns t as address valid to cs low 0 ns t ah address valid after cs high 0 ns t ld ldac delay from cs high 10 ns t ds data valid to cs low 0 ns t dh data valid after cs high 0 ns t lwd ldac low 50 ns t reset reset low time 50 ns t s settling time 10 m s table ii. timing specifications (t a = C40 c to +85 c). figure 4. digital input and output timing. t rcs cs t rds t rdh t as t csd t dz t ah r/w a0/a1 data out data valid data read timing 0.012% of fsr error band 0.012% of fsr error band mid-scale reset v out , dac7725 +fs ?s v out , dac7724 +fs ?s dac7724/25 reset timing t reset t s t wcs cs t ws t as t ah t wh r/w a0/a1 t s 0.012% of fsr error band 0.012% of fsr error band ldac t ds t dh data in v out data write timing t lwd t ld

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